White Papers
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The Top 5 Biggest Design for Manufacturability Issues
Wish you could cut time out of your product development cycle? One way to do it is to address design for manufacturability (DFM) as early as possible. Here is our Top Five list of common DFM issues. Use it as a checklist on your next project.
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Attack the stack: Identifying unauthorized code execution caused by buffer overflows
Nearly half of all critical security leaks in embedded software are due to heap overflows. Stack-based buffer overflows account for a smaller percentage, but are exploited with the same technique to inject and execute unauthorized code or change execution flow. Instead of policing such attacks to manage security risk, a better approach is to use the strength of quality software development and code testing with static analysis to find and fix the underlying defects that lead to security vulnerability.
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SCADE System, a comprehensive toolset for smooth transition from Model-Based System Engineering to certified embedded control and display software
The International Council on Systems Engineering (INCOSE) defines system engineering as an interdisciplinary approach and means to enable the realization of successful systems. It focuses on defining customer needs and required functionality early in the development cycle, documenting requirements, and then proceeding with design synthesis and system validation. The main challenges of system engineering are related to providing non-ambiguous and coherent specification, making all relevant information readily available to all stakeholders, establishing traceability between all activities, and providing the appropriate level of verification and validation. Tools supporting these activities in an efficient way are not yet widely deployed in the industry.
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10 Ways to Reduce Time in Product Development
How can product development teams reduce product development time even when internal resources have been cut?
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Network Applications and the Impact on Corporate WANs
Enterprises expect more from their communications networks than ever before.
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VPX for High-Performance Avionic Computers
Traditional high-performance computing platforms are limited by the connection bandwidth and latency between the multiple computing elements needed to achieve the performance targets. For the embedded market, the difficulty is compounded by the demanding environmental requirements. The VPX standard resolves this limitation with a large number of high-throughput point-to-point connections between the processing elements in a rugged mechanical structure.
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FPGAs for Speed and Flexibility
Benefits of FPGA Modules derived from their Speed and Flexibility - You Can't Do More for Less
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Integrating High-Level Synthesis Designs into SoCs with Less Effort and Risk
High-Level Synthesis (HLS) tools have become increasingly popular for creating ASIC and FPGA hardware with less effort and risk. The productivity gains can be very high, especially when starting from higher abstraction levels like that of Synphony Model Compiler, which uses the Simulink(r) environment and a high-level IP model library for design capture. However, when it comes to integrating an HLS design into a surrounding system or system-on-chip (SoC), the manual effort of interface integration, re-verification and the subsequent risks of errors, debugging and project delay can significantly diminish the HLS productivity gains.
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Load balancing in ATCA platforms
Two methods for "taking the load off" of your ATCA network element, one using the internal switch and one through software, offer solutions for optimized packet processing for network services.
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OpenVPX System Bandwidth
A comparison of 10Gb Ethernet Performance, Serial Rapid IO, and InfiniBand.
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Cable IPv6 Transition
Ravenous consumption of IP addresses with the recent surge in IP-enabled devices are forcing Mobile Service Operators to transition from the long-time Internet Protocol, IPv4, to it's replacement, IPv6.
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Survey: Companies Look to the Cloud for Data Integration
An application example explaining how one company integrated its data into "the cloud."
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Capture, Decode and Debug of Low Speed Serial Buses
Low speed serial bus validation requires more than simple voltage verses time measurements. LeCroy oscilloscopes have the ability to use a wide range of triggering, analysis and decode capabilities to bring increased confidence to the validation process. This article will cover methods to capture, view, decode and debug a variety of low speed serial data protocols including RS232, generic UARTs, I2C, CAN, Flexray, LIN, ARINC 429, MIL-STD-1553, MIPI DPHY, DigRF 3G, DigRF v4 and Audio applications (I2S, LJ, RJ and TDM).
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Testing & Debugging Avionics Systems that Use ARINC 429 or MIL-STD-1553 Data Busses
The data busses in aircraft and spacecraft require very high quality in transmission and reception since proper communication of commands and data are crucial to operation. The ARINC 429 standard used predominately in commercial aircraft and the MIL-STD-1553 bus used in military avionics and space vehicles (military and commercial) have some common characteristics as well as important differences. This paper will give useful examples of how to view, test and troubleshoot these busses using digital oscilloscopes.
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Methods and Tools for Bring-Up and Debug of an FPGA-Based ASIC Prototype
Software simulation of RTL is no longer capable of providing all of the verification required for today's complex ASIC designs. Modern ASICs are a complex mixture of hardware and software, so it is necessary to verify the design within the context of the complete system, running the full range of software at speeds that approach real-time. Successfully validating an ASIC design on an FPGA-based prototype before committing to silicon is now a key project milestone for most design teams. This paper examines some of the best practices for both successful bring-up and logic debug of ASICs using FPGA-based prototypes.
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Examine the Hidden Costs of Commercial PC Platforms in Embedded Applications
In this challenging global economy, system integrators are facing growing pressure to lower costs, accelerate Time-to-Market (TTM), and maximize profits while reducing risk. This white paper explores the hidden costs of commercially available PC platforms when used in embedded applications and why today's embedded platforms are a superior choice for your next high-end embedded application. Included are the common myths and misconceptions of today's embedded platforms. We need to clearly differentiate today's embedded solutions from those of 5 or 10 years ago and recognize the dramatic evolution that is currently taking place in embedded technology.
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Botnets: The dark side of cloud computing
Security gateways can offer protection against malicious botnets that can tarnish your cloud network.
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Enabling 10Gbit-Ethernet in Miniature I/O Connectors for Aerospace and Defense Applications
The CeeLok FAS-T connector, a new high-speed circular I/O, combines the ruggedness of a MIL-C-38999-style design with an insert specifically configured for 10 Gbit-Ethernet transmission. Additionally, it is a small-form-factor connector system that is field repairable and supports data rate requirements for current and next-generation electronic systems in Aerospace and Defense applications.
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Developing Software in a Multicore and Multiprocessor World
Software developers stand to gain increased speed and functionality from multiprocessor architectures, but the resulting complexity makes detecting software errors more challenging. Read this technical paper for an overview of the challenges associated with software development on next-gen architectures and learn how static analysis can help.
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RDMA: The Future of High-Speed Fabric Interconnects
This white paper will explore the merits of InfiniBand architecture as well as methods of optimizing its use.
Staff, XO Communications
Staff, Radisys
Staff, Computer World
Dr. Michael Lauterbach, LeCroy Corporation
Earle Olson, TE Connectivity
