In the past, digital signal processing tasks were commonly realized in software running on dedicated DSP processors. However, these are limited to more sequential architectures that require extremely high clock speeds and consume a lot of power. Direct implementation of these algorithms in silicon, however, offers more choices in parallelism with lower clock speeds and power consumption. As a result, an increasing amount of Application-Specific Integrated Circuit (ASIC) or a Field-Programmable Gate Array (FPGA) design projects include algorithmic subsystems that are implementing mathematical DSP behavior directly in logic. These subsystems are beginning to dominate the functional content chips in certain application domains.
This paper will describe the key technologies of Synphony HLS and their benefits to algorithm, system,
hardware, and verification engineers.